Introduction to 5-Level Paging in 3rd Gen Intel Xeon Scalable Processors with Linux

5-level paging is a new paging mode of x86_64 processors in EM64T mode. As its name suggests, 5-level paging will translate linear addresses by traversing a 5-level hierarchy of paging structures. Compared to the traditional 4-level paging, 5-level paging extends the processor’s linear-address width to 57 bits from 48 bits, thereby giving the processor and applications access to an even larger amount of memory.

This paper introduces the background of 5-level paging function from both the hardware and software perspective. It also explains how to enable or disable this function in the Linux kernel and how to verify that the function is working properly.

This paper is for administrators and application programmers. An understanding of x86 multilevel paging mechanism and basic rules of memory management is useful for the underlying implementation of this feature.

Introduction
Enabling and verifying 5-level paging in Linux
Disabling 5-level paging
Test case for 5-level and 4-level paging
Summary
References
Author

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Related product families

Product families related to this document are the following:

• Memory
• Processors